1. Field of the Invention
This invention relates to non-volatile semiconductor memory devices and particularly to a non-volatile semiconductor memory device having means for detecting individually deterioration of the threshold voltage of a plurality of memory cells constituting the non-volatile semiconductor memory device.
2. Description of the Related Art
The prior art Documents related to the present invention are listed below.
Document 1: "A 16 Kb Electrically Erasable Nonvolatile Memory", 1980 IEEE ISSCC Dig. Tech. Pap. pp. 152-153, 271, 1980. PA1 Document 2: "Analysis and Modeling of Floating-Gate EEPROM Cells" IEEE Trans. Electron Devices June 1986, ED-33, No.6, pp. 835-844. PA1 Document 3: "Semiconductor MOS Memory and Method of Using the Same", Nikkan Kogyo Newspaper Co., 1990, pp. 96-101. PA1 Document 4: "A Novel Cell Structure Suitable For A 3 Volt Operation, Sector Erase Flash Memory" IEDM 92, pp. 599-602 (1992). PA1 Document 5: "Flash EEPROM Memory Systems Having Multistate Storage Cells" U.S. Pat. No. 5,043,940 (1991). PA1 Document 6: "Semiconductor Memory Device with Self-Correcting Function and Microcomputer" Patent Laid-open Gazette No. 1-133300(1989) corresponding to U.S. Pat. No. 4,901,320.
A non-volatile semiconductor memory device (hereinafter, referred to as PROM) of which the recorded data is not lost even if the power supply is turned off has already been developed and practically used since the early 1970's. In addition, another non-volatile semiconductor memory device (hereinafter, referred to as EEPROM) which is electrically erasable, as described in the Document 1, has been practically used since the 1980's.
In the write operation of a memory cell of the EEPROM, the transistor-structure memory cell having a floating gate is charged and discharged with electrons through a thin insulating oxide film by the Fowler-Nordheim tunneling effect, so that the threshold voltage of the transistor is controlled (see Documents 1 and 2). The threshold of the memory cell is increased by injecting electrons into the floating gate and decreased by discharging electrons or injecting holes.
For example, FIG. 2 in Document 3 shows the functional circuit blocks of this EEPROM. FIG. 7 in this document is a circuit block diagram of the conventional EEPROM which is given for the comparison with this invention.
In FIG. 7 there are shown 32 memory cells in four rows and eight columns in which two bits of data are simultaneously read and programmed. In order to selectively make programming, erasing and reading for the 32 memory cells, it is necessary to provide, as illustrated, decoder circuits, multiplexers, address buffers, a chip control circuit, a high-voltage generation/control circuit, programming circuits, a sense circuits, data input buffers and data output buffers.
In FIG. 7 there are also shown address input terminals 501, 502, 503 and 504 which are used for inputting the address data for the memory cells selected by row lines and column lines. Input terminals 505, 506 and 507 are used for inputting control signals for controlling the operation mode of the EEPROM; that is, the input terminal 505 is used for inputting a chip selection signal, the input terminal 506 for inputting an output selection signal, and the input terminal 507 for inputting a write signal. There are shown input/output terminals 508 and 509 from which the stored data of the selected memory cells are produced in the read mode and to which the data to be stored in the memory cells are supplied in the write mode. Address buffers 511, 512, 513 and 514 have the function to buffer and output the address data and to receive the power-down signal and reduce the current consumption in the input portion. In another conventional technique (as disclosed in Document 3), the address buffers are additionally provided with the function of latching the address data in response to a latch signal in the write mode.
A chip control circuit 515 is responsive to the control signals at the control input terminals 505, 506 and 507 to select the read mode, write mode, power-down mode (or standby mode) and output nonselection mode. The write mode is further divided into two modes, or the erase mode and the program mode. In the erase mode, the memory cells of a byte or a row or a memory block, to which the selected memory cell belongs, are made to the erased state in order to alter the data stored in the selected memory cell. The erased state of the memory cell means that the threshold of the memory cell is higher (or lower) than the gate voltage applied thereto in the read mode. In the program mode, the selected memory cell is made to the programmed state in accordance with the input data. The programmed state means that the threshold of the memory cell is lower (or higher) than the gate voltage applied thereto in the read mode. When the memory cell data is altered, the memory cell is first brought to the erase state in the erase mode and then brought to the programmed state in accordance with the input data. In other words, the write mode includes the erase mode and the program mode. The chip control circuit 515 also includes a function of terminating the erase mode or the program mode automatically in accordance with the internal timer.
A high-voltage generation/control circuit 518 has a circuit for increasing the power supply voltage supplied to the EEPROM in the write mode to generate a high voltage of about 10 through 25 V (referred to as charge pump circuit), and a control circuit for supplying desired high voltages to the circuits of the EEPROM in accordance with the erase mode and program mode.
A row decoder 516 decodes the outputs from the address buffers 511 and 512 and applies a high (H) voltage only to the row line (the word line) of the selected memory cell and a low (L) voltage to the row lines of the non-selected cells. The high voltage for selection is about the power supply voltage in the read mode and a high voltage in the write mode.
A column decoder 517 decodes the outputs from the address buffers 513, 514 and supplies a high voltage to the column line of a selected memory cell and a low voltage to the column lines of the non-selected memory cells through a multiplexer 527 or 528. The multiplexer 527 or 528 connects the selected column line (bit line) to be data line 597 or 598 in accordance with the signals from the column decoder 517. The output voltage from the column decoder 517 is about the power supply voltage in the read mode and a high voltage in the write mode.
There are shown row lines 529, 530, 531 and 532, and column lines 533, 534, 535, 536, 537, 538, 539 and 540. There are also shown memory sense program lines 577, 578, 579 and 580, and memory cells 545, 546, . . . , 576. Each memory cell includes one select transistor and one memory transistor and has the same structure and connection as shown in FIGS. 2 and 3 of Document 1. For example, the row line is connected to the gate of the select transistor, the column line to the drain of the select transistor, the memory sense program line to the gate of the memory transistor and a source line 604 to the source of the memory transistor.
In the write mode, a data input buffer 520 or 524 buffers the input data from the input/output terminal 508 or 509 and supplies it to a program circuit 519 or 523. The data input buffer may function to latch the input data in the write mode, in response to a latch signal.
The program circuit 519 or 523 receives a signal of program mode and a high voltage and supplies a high voltage or low voltage depending on the input data to the data line 597, 598. In this case, the conventional EEPROM can produce only one high voltage and one low voltage (normally 0 V).
A sense circuit 521, 525 detects and amplifies the voltage value or current value on the data line 597, 598 to which the data of the selected memory cell is transmitted through a column line and a multiplexer in the read mode. Then, the amplified voltage or current is outputted to a data output buffer.
A data output buffer 522, 526 receives the data from the sense circuit and supplies it to the output terminal in the read mode. Also it functions to inhibit the output in the power-down mode and the output non-selection mode.
In FIG. 7, reference numeral 581 is the output from the address buffer 511 and the input to the row decoder 516, 582 is the output from the address buffer 512 and the input to the row decoder 516, and 583 is the output from the address buffer 513 and the input to the column decoder 517. Shown at 584 is the output from the address buffer 514 and the input to the column decoder 517 and 585 through 588 are the outputs from the column decoder 517 and the inputs to the multiplexers 527 and 528. Shown at 603 is the power down signal from the chip control circuit 515. This signal is supplied to the control input terminals of the address buffers 511, 512, 513, 514. Shown at 589 is a read enable signal for activating or inactivating the sense circuits 521, 525. Shown at 590 is the program signal which, in the program mode, activates the program circuits 519, 523 and causes the high-voltage generation/control circuit 518 to generate high voltages on high voltage lines 594 and 596 and 0 V on a memory sense line 595. Shown at 591 is the erase signal for causing the high-voltage generation/control circuit 518 to generate high voltages at the outputs 594 and 595. Reference numeral 592 denotes a data input enable signal for activating the data input buffers 520, 524 in the write mode, and 593 a data output enable signal for activating the data output buffers 522, 526 in the read mode.
A first high voltage signal 594 of a high voltage is supplied to the row decoder 516 and the column decoder 517 in the write mode. A memory sense line 595 is at 0 V in the program mode, at a high voltage in the erase mode and at a voltage between 0 V and the power supply voltage in the reading mode. A second high voltage signal line 596 is at a high voltage in the program mode. An output 599 from the data input buffer 520 is fed to the input of the program circuit 519. An output 601 from the data input buffer 524 is fed to the input of the program circuit 523. An output 600 from the sense circuit 521 is fed to the input of the data output buffer 522. An output 602 from the sense circuit 525 is fed to the input of the data output buffer 526. Circuits 541, 542, 543 and 544 decode the signal 595 according to the signals on the row lines 529,530, 531 and 532 into memory sense program signals 577, 578, 579 and 580.
The write operation and read operation of the conventional EEPROM will be described briefly.
In the read operation, the control signals from the control input terminals 505, 506 and 507 are rendered to the read mode and the selected address data are applied to the address input terminals 501, 502, 503 and 504. The input address data are held by the address buffers 511, 512, 513 and 514, and decoded by the row decoder 516 and column decoder 517. A selected one of the four output signal lines of the row decoder 516 which are respectively connected to the row lines is at a high voltage (normally about the power supply voltage), and the other three signal lines are at a low voltage. In addition, one column line is selected from the column lines 533 through 536 by the outputs 585 through 588 of the column decoder 517 through the multiplexer 527. Only the selected column line is electrically connected to the data line 597 through a low impedance. Similarly, one of the column lines 537 through 540 is selected by the outputs 595 through 588 through the multiplexer 528. At this time, a voltage of, for example, 2 through 4 V for detecting the threshold value of the memory cell is outputted to the memory sense line 595, and fed through the circuits 541 through 544 to only the selected one of the memory sense program lines. The memory ground line 604 is in the grounded state. The voltage from the sense circuit 521, 525 is supplied to the column line of the selected memory cell. When the threshold voltage of the memory cell is lower than the threshold detection voltage, the memory cell transistor is turned on and thus a current flows from the column line to the memory ground line 604. When the threshold voltage of the memory cell is higher than the threshold detection voltage, the selected memory cell transistor is turned off and thus no current flows from the column line to the memory ground line 604. The voltage on the column line is set by the sense circuit and the current to the column line in the read mode is supplied from the sense circuit. When this current is detected and amplified by the sense circuit, the stored data in the memory cell is produced on the line 600, 602 in a binary value of high or low voltage and fed through the data output buffer 522, 526 to the outside. If the threshold value of the memory cell is as high as 6 V, a high voltage is produced at the input/output terminal 508. If the threshold value of the memory cell is as low as 0 V, a low voltage is produced at the input/output terminal 508.
In the write operation, the data in the memory cell is erased first. In this prior art, the data erasing is normally made with a unit of one row line, but may be made with a unit of one byte or block. Although the erase mode in the prior art is effected by the control input to the input terminals 505, 506, 507, it is also possible to effect the erase mode by the input data to the data input buffer in addition to the control inputs. In the erase mode, the row line of the memory cell is selected by the address data from the address input terminals 501, 502. The line 594 is kept at a high voltage and the row line of the selected memory cell is at a high voltage, and 0 V is fed to the row lines of the other memory cells. In addition, the line 595 is at a high voltage and the memory sense program line of the row line of the selected memory cell is at a high voltage by the circuits 541 through 544. The sense circuits and program circuits 519, 521, 523 and 525 are inactivated in the erasing mode, and the line 597 is at 0 V or in the floating state. The memory ground line 604 is grounded in the erasing mode. Thus, a high voltage (for example, 20 V) is applied to the gate of the memory cell of the selected row line, and the drain and source are grounded. At this time, the Fowler-Nordheim tunnelling effect occurs causing injection of electrons from the drain into the floating gate so that the threshold value of the memory cell transistor becomes high (for example, 5 through 8 V).
When the erased memory cell is programmed, the program mode is inputted and the address data for program is supplied to the address input terminals 501, 502, 503, 504. In the program mode, the line 594 is at a high voltage, the line 595 is at 0 V, the line 596 is at a high voltage and the line 604 is in the floating state. The row decoder 516, the column decoder 517, the program circuit 519, 523 and the data input buffer 520, 524 are activated and the sense circuits 521, 525 and the data output buffers 522 and 526 are inactivated. If a low voltage is supplied as input data to the input terminal 508, the program circuit 519 produces a high voltage (for example, 20 V) on the output line 597, and if a high voltage is supplied to the input terminal 508, it produces 0 V on the line 597. When the line 597 is at a high voltage, the selected column line is at a high voltage (for example, 20 V) since the selected one of the outputs 585 through 588 from the column decoder is also at a high voltage. The selected row line is also at a high voltage and the memory sense program lines are at 0 V. Thus, the gate of the memory cell transistor is at 0 V and the drain is at a high voltage (for example, 20 V). At this time, the Fowler-Nordheim tunnelling effect causes discharge of electrons from the floating gate to the drain and injection of holes from the drain into the floating gate so that the threshold voltage of the memory cell transistor is reduced to, for example, -3 V to 0 V.
The Fowler-Nordheim tunnel current for storage principle in the conventional EEPROM is proportional to the electric field applied across the insulating film as expressed by the equation (1) of Document 2. The threshold value of the memory cell transistor is changed linearly with the high voltage in the erase or program mode as shown in, for example, in FIGS. 6 and 9 of Document 2. In the conventional EEPROM, only one high voltage value is used in the erase mode or the program mode. Even in the read mode, only a binary value of high or low can be detected.
Moreover, Document 6 discloses a circuit for and a method of detecting variation of the threshold voltage upon programming and erasing of a binary level. However, in this circuit and method, another memory cell for parity information different from those for program data is required in order to detect and correct variation of the data. A variation detection method in programming of a memory cell with four or more values has not been disclosed yet.
In the parent application, that is U.S. patent application Ser. No. 08/216,874 filed on Mar. 23, 1994, entitled "Non-volatile Semiconductor Device and a Method of Using the Same", at least three different data can be written in or read from each memory cell. In the parent application, one of a plurality of bits representing data of, for example, one byte which are written in a plurality of memory cells is used as a parity bit in order to check an error in writing or reading the data in or from the plurality of memory cells. This application is a continuation-in-part of the parent application and the contents of the parent application are incorporated herein by reference. It should be noted, however, that the terms "column" and "row" are used in this application in place of "row" and "column", respectively, used in the parent application.
In the conventional EEPROM and flash memory, when the number of altering repetitions is increased, the gate insulating film is deteriorated to reduce the amount of electricity stored in the memory cell with the result that the threshold voltage is decreased with time. When this threshold voltage is reduced to less than the level for judging "0" or "1" in the binary memory, the written data cannot be correctly read. In U.S. Pat. No. 4,901,320, a parity bit is provided to each word for correcting data error, but it does not concerned particularly with the reduction of the threshold voltage in the individual bit of each word. Therefore, even though the memory cell providing a bit of the word has its threshold voltage so reduced that it already becomes inappropriate for writing, that cell is still used, thus lowering the reliability of the whole system. Moreover, JP-A-3-288400 describes the technique for preventing the effect of the threshold voltage reduction of a reference cell with time, but it does not consider particularly the reduction of the threshold voltage in the individual bit of the word.
This problem is particularly serious in a non-volatile semiconductor memory device constructed to store at least three different data in one memory cell as disclosed in, for example, the parent application, because at least three different threshold values of the memory cell corresponding to different data are close to each other.